1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device with a high voltage transistor.
2. Description of the Related Art
In a design of a transistor to which a high-level voltage is supplied (hereafter, referred to as a high voltage transistor), to prevent a contact melting phenomenon, regulations on the layout of the high voltage transistor have been enacted and complied. Hereinafter, the high voltage refers to a voltage high enough to melt a contact when the voltage is supplied to one end of the contact and a ground voltage is supplied to the other end of the contact. In general, the level of the high voltage may be at least 3V, and may be about 20V at its highest level. The high voltage is generated in the semiconductor device through charge pumping using a power supply voltage that is input from an outside of the semiconductor device.
FIGS. 1A to 1C are layout views illustrating a forbidden layout (FIG. 1A) and recommended layouts (FIGS. 1B and 1C). Further, FIGS. 2A to 2C are circuit diagrams illustrating transistors 110 and 120 shown in FIGS. 1A to 1C, respectively.
Referring to FIG. 1A, a high voltage VPP is supplied to one junction 111 of a drain and a source of the transistor 110, and a ground voltage VSS is supplied to the other junction 112 thereof. Further, the high voltage VPP is supplied to one junction 121 of a drain and a source of the transistor 120, and the ground voltage VSS is supplied to the other junction 122 thereof. A voltage INPUT_A is supplied to a gate of the transistor 110 and a voltage INPUT_B is supplied to a gate of the transistor 120. The junction 112 of the transistor 110, to which the ground voltage VSS is supplied, and the junction 121 of the transistor 120, to which the high voltage VPP is supplied, are adjacent to each other. Since the voltage difference between the adjacent junctions 112 and 121 is as high as the high voltage VPP, the contact melting may occur between the junctions 112 and 121, and thus the layout shown in FIG. 1A is not used.
Referring to FIG. 13, the junction 111 of the transistor 110 and the junction 121 of the transistor 120 are shared. Since the high voltage VPP is identically supplied to the junctions 111 and 121, the voltage difference between the junctions 111 and 121 becomes 0V. Accordingly, in the layout of FIG. 1B, the contact melting may not occur, and the layout is used as a recommended layout (or guide layout).
Referring to FIG. 1C, the junction 112 of the transistor 110 and the junction 122 of the transistor 120 are disposed adjacent to each other. Since the voltage difference between the adjacent junctions 112 and 122 is 0V, the contact melting may not occur in the layout. Accordingly, the layout shown in FIG. 1C is also used as the recommended layout. For reference, the junctions 112 and 122 of the transistors 110 and 120 may be designed to be shared.
As described above, the high voltage transistor should be designed along the recommended layout to avoid the forbidden layout. However, in the case where the design is made to be complied with only the recommended layout, there are many limitations in the degree of freedom of the design, and more fundamental solution to the above concerns is in demand.